1. Field of the Invention
The invention disclosed broadly relates to memory addressing in a computer and more particularly relates to a paged virtual memory addressing scheme within a computer system.
2. Background Art
In computer memory systems, the instruction set calls for a fixed number of bits of memory addresses such as 16, yet larger memory regions are often required to store the necessary information. The solution is to use virtual memory--the 16 address bits mapped to a larger memory area. To do this, a logical address is often mapped to a physical address through a page translation random access memory (RAM). The 16 bit logical address may, for example, consist of a most significant 4 bit field which can be expanded to 11 most significant physical address bits through a page translation RAM and a 12 bit page address field which is used directly as the 12 least significant bits of the physical address. Thus, the 4 most significant logical address bits will access the physical address corresponding to a 4 k region of memory called the page. This 4 k region is addressable by the other 12 bits in the 16 bit address.
The translation logic is complicated because page addresses are mapped differently for instructions and operands. This implies two page translation RAMs, which will not fit on a single instruction dispatch integrated circuit chip. As a result, they are placed on the address translation and exception handling chips of the computer system. The biggest concern of this partitioning is the performance impact because of the frequency of address translation in any given instruction mix. The delay incurred by placing the translation RAMs on two different integrated circuit chips needs to be minimized.